Adder with Efficient Speed and Area by Using Quantum-Dot Cellular Automata Technology
Author : G. Sumana and G. Anjan BabuVolume 8 No.3 Special Issue:June 2019 pp 109-113
Abstract
The lessening in transistor estimate by following field’s law made chip unpredictability with more computational capacity. The present size of the transistor needs to decrease more, which prompts nanotechnology. The quantum-dot cell automata come extremely close to nanotechnology presents one of the conceivable arrangements in defeat this physical breaking point, even though the designs with QCA technology are not a fundamental basic. In this brief by considering quantum-dot cell automata (QCA) innovation idea a greater part door based adder is outlined. The effectiveness in territory and speed by larger part entryway idea based adders are executed and contrasted with beforehand technique plans by utilizing verilog coding mimicked in Xilinx. The proposed one-piece QCA viper depends on another calculation that requires just three larger part entryways and two inverters for the QCA expansion. Novel 128-bit adders designed in QCA become accomplished.
Keywords
QCA, Nanotechnology, Majority gates (MG), adder, Verilog HDL
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References
[1] B.W.Y. Wei and C.D. Thompson, “Area-Time Optimal Adder Design”, IEEE Trans., C- 39, No.5, pp. 666-675, May 1990.
[2] Earl E. Swartzlander, “Computer Arithmetic” Vol. 1 & 2, IEEE Computer Society Press, 1990.
[3] “Computer Arithmetic: Principles, Architecture and Design”, John Wiley and Sons, 1979.
[4] S. Waser, and M. Flynn, “Introduction to Arithmetic for Digital Systems Designers”, Holt, Rinehart and Winston 1982.
[5] Z. Tu, W. Liang.î 16-bit Different Structures Skip Carry Adderî. Australian National University,2006
[6] R. Rosemark, W.C. Lee, B. Urgaonkar, ìOptimizing Simulation of Ripple carry adderî
[7] M. Janez, P. Pecar, and M. Mraz, “Layout design of manufacturable quantum-dot cellular automata,” Microelectron. J., Vol. 43, pp. 501–513, 2012.
[8] KhabiaSumantKatiyal, K.K. Choudhary, Automata NileshPatidar, Namit Gupta, and Amita “A Novel 4-Bit Arithmetic Logic Unit Implementation in Quantum-Dot Cellular”
[9] “Design, Layout and Simulation of 8 Bit Arithmetic and Logic Unit Using C5 Process Technology” Priyal Grover1, Assistant Professor Hemantverma Department of Electronics and Communication Engineering Technocrats Institute Of Technology, Rajiv Gandhi Proudyogiki Vishwa vidyalaya, Bhopal.
[10] V. Pudi and K. Sridhar an, “Efficient design of a hybrid adder in quantum dot cellular automata,” IEEE Trans. Very Large Scalentegr (VLSI) Syst., Vol. 19, No. 9, pp. 1535–1548, Sep. 2011.
[11] S. R. Sahoo and K. K. Mahapatra „‟Design of low power and high speed ripple carry adder using modified feed through logic‟‟ IEEE (CODIS), 2012 International.
[12] Fu-Chiung Cheng Stephen H. Unger “Delay-Insensitive Carry-Look ahead Adders”
[13] W. Liu, L. Lu, M. O‟Neill, and E. E. Swartz lander, Jr., “Design rules for quantum-dot cellular automata,” In Proc. IEEE Int. Symp. Circuits Syst., pp. 2361–2364, May 2011.
[14] K. Kong, Y. Shang, and R. Lu, “An optimized majority logic synthesis methodology for quantum-dot cellular automata,” IEEE Trans. Nanotechnol., Vol. 9, No. 2, pp. 170–183, Mar. 2010.