Asian Journal of Engineering and Applied Technology (AJEAT)
FPGA Implementation of Reversible Adder/Subtractor
Author : Gowthami. P and R.V.S. SatyanarayanaVolume 7 No.2 July-December 2018 pp 16-20
Abstract
This work presents the new design of the reversible adder/subtractor circuit. The proposed design of reversible adder/subtractor is compared to the existing counterpart in terms of design constraints such as the total number of reversible gates, no. of constant inputs and quantum cost. The delay and power of the proposed reversible adder/subtractor circuit were calculated, compared with existing reversible and conventional adder/subtractors.
Keywords
Reversible Adder/Subtractor, Reversible gates
Full Text:
References
[1] R Landauer, “Irreversibility and heat generation in the computing process”, IBM Journal of Research and Development, Vol. 5, pp.183-191, 1961.
[2] C.H. Bennett, “Logical reversibility of Computation”, IBM Journal of Research and Development, Vol.17, pp. 525-532, 1973.
[3] M. Nielsen and I. Chuang, “Quantum Computation and Quantum Information”, Cambridge Univ. Press, 2000.
[4] C. H. Bennett, Notes on the history of reversible computation, IBM Journal of Research and Development, Vol. 32, pp.16-23, 1988.
[5] N. Al-Rabadi, “Reversible Logic Synthesis: From Fundamentals to Quantum Computing”.
[6] Saha A, and Manna N, “Digital Principles and Logic Design”, Infinity Science Press LLC, 2007.
[7] Anil k. Maini, “Digital Electronics. Principles. Devices and Applications”, John Wiley & Sons, 2007.
[8] M Haghparast, L Rezazadeh and V Seivani, “Design and Optimization of Nanometric Reversible 4 Bit Numerical Comparator”, Middle-East Journal of Scientific Research, Vol. 7, pp. 581-584, 2011.
[9] B Parhami, “Fault Tolerant Reversible Circuits”, Proc. 40th Asilomar Conf. Signals, Systems and Computers, Pacific Grove, CA, 2006.
[10] M Haghparast, and K. A Navi, “Novel reversible BCD adder for nanotechnology based systems”, American Journal of Applied Sciences, Vol. 5, pp. 282-288, 2008.
[11] H.G Rangaraju, U Venugopal, K.N Muralidhara, and K.B Raja, “Design of efficient reversible parallel Binary adder/subtractor”, Springer-Verlag Berlin Heidelberg, CNC 2011, CCIS 142, 2011, pp. 83–87.
[12] P Gowthami and R.V.S. Satyanarayana, “An Improved Design of Reversible Adder/ Subtractor”, International Journal of Engineering & Technology (IJET), Vol. 7, No. 2.12, Special Issue 12, 2018.
[13] Genesys Reference Manual available at:
https://www.xilinx.com/support/documentation/university/XUP%20Boards/XUPGenesys/documentation/Genesys_RM_VC.pdf