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Home»Articles»FPGA Implementation of Reversible Adder/Subtractor

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Asian Journal of Engineering and Applied Technology (AJEAT)

Editor Dr. Seshadri Ramkumar
Print ISSN : 2249-068X
Frequency : Quarterly

FPGA Implementation of Reversible Adder/Subtractor

Author : Gowthami. P and R.V.S. Satyanarayana
Volume 7 No.2 July-December 2018 pp 16-20

Abstract

This work presents the new design of the reversible adder/subtractor circuit. The proposed design of reversible adder/subtractor is compared to the existing counterpart in terms of design constraints such as the total number of reversible gates, no. of constant inputs and quantum cost. The delay and power of the proposed reversible adder/subtractor circuit were calculated, compared with existing reversible and conventional adder/subtractors.

Keywords

Reversible Adder/Subtractor, Reversible gates

Full Text:

References

[1] R Landauer, “Irreversibility and heat generation in the computing process”, IBM Journal of Research and Development, Vol. 5, pp.183-191, 1961.
[2] C.H. Bennett, “Logical reversibility of Computation”, IBM Journal of Research and Development, Vol.17, pp. 525-532, 1973.
[3] M. Nielsen and I. Chuang, “Quantum Computation and Quantum Information”, Cambridge Univ. Press, 2000.
[4] C. H. Bennett, Notes on the history of reversible computation, IBM Journal of Research and Development, Vol. 32, pp.16-23, 1988.
[5] N. Al-Rabadi, “Reversible Logic Synthesis: From Fundamentals to Quantum Computing”.
[6] Saha A, and Manna N, “Digital Principles and Logic Design”, Infinity Science Press LLC, 2007.
[7] Anil k. Maini, “Digital Electronics. Principles. Devices and Applications”, John Wiley & Sons, 2007.
[8] M Haghparast, L Rezazadeh and V Seivani, “Design and Optimization of Nanometric Reversible 4 Bit Numerical Comparator”, Middle-East Journal of Scientific Research, Vol. 7, pp. 581-584, 2011.
[9] B Parhami, “Fault Tolerant Reversible Circuits”, Proc. 40th Asilomar Conf. Signals, Systems and Computers, Pacific Grove, CA, 2006.
[10] M Haghparast, and K. A Navi, “Novel reversible BCD adder for nanotechnology based systems”, American Journal of Applied Sciences, Vol. 5, pp. 282-288, 2008.
[11] H.G Rangaraju, U Venugopal, K.N Muralidhara, and K.B Raja, “Design of efficient reversible parallel Binary adder/subtractor”, Springer-Verlag Berlin Heidelberg, CNC 2011, CCIS 142, 2011, pp. 83–87.
[12] P Gowthami and R.V.S. Satyanarayana, “An Improved Design of Reversible Adder/ Subtractor”, International Journal of Engineering & Technology (IJET), Vol. 7, No. 2.12, Special Issue 12, 2018.
[13] Genesys Reference Manual available at:
https://www.xilinx.com/support/documentation/university/XUP%20Boards/XUPGenesys/documentation/Genesys_RM_VC.pdf

Asian Journal of Engineering and Applied Technology is a peer-reviewed International research journal aiming at promoting and publishing original high quality research in all disciplines of engineering and applied technology. All research articles submitted to AJEAT should be original in nature, never previously published in any journal or presented in a conference or undergoing such process across the world. All the submissions will be peer-reviewed by the panel of experts associated with particular field. Submitted papers should meet the internationally accepted criteria and manuscripts should follow the style of the journal for the purpose of both reviewing and editing.

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Chemical engineering
Civil engineering
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Computer science and information science
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Industrial engineering
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Textile & Fashion Technology

This work presents the new design of the reversible adder/subtractor circuit. The proposed design of reversible adder/subtractor is compared to the existing counterpart in terms of design constraints such as the total number of reversible gates, no. of constant inputs and quantum cost. The delay and power of the proposed reversible adder/subtractor circuit were calculated, compared with existing reversible and conventional adder/subtractors.

Editor-in-Chief
Dr. Seshadri Ramkumar
Department of Environmental Toxicology, Texas Tech University, Texas
[email protected]
Editorial Advisory Board
Dr. Kamarul Ariffin Bin Noordin
Department of Electrical Engineering, University of Malaya, Malaysia
[email protected]
Dr. Benjamin T.F. Chung
Department of Mechanical Engineering, University of Akron, Akron, USA
[email protected]
Dr. Mohd Faiz Bin Mohd Salleh
Department of Electrical Engineering, University of Malaya, Malaysia
[email protected]
Dr. Suhana Binti Mohd Said
Department of Electrical Engineering, University of Malaya, Malaysia
[email protected]
Dr. Norrima Binti Mokhtar
Department of Electrical Engineering, University of Malaya, Malaysia
[email protected]
Dr. Mohamadariff
Department of Electrical Engineering, University of Malaya, Malaysia
[email protected]

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    Editorial Note

    Editorial Dr. Seshadri Ramkumar

    Editor-in-Chief
    Dr. Seshadri Ramkumar
    Department of Environmental Toxicology, Texas Tech University, Texas
    [email protected]
    Editorial Advisory Board
    Dr. Kamarul Ariffin Bin Noordin
    Department of Electrical Engineering, University of Malaya, Malaysia
    [email protected]
    Dr. Benjamin T.F. Chung
    Department of Mechanical Engineering, University of Akron, Akron, USA
    [email protected]
    Dr. Mohd Faiz Bin Mohd Salleh
    Department of Electrical Engineering, University of Malaya, Malaysia
    [email protected]
    Dr. Suhana Binti Mohd Said
    Department of Electrical Engineering, University of Malaya, Malaysia
    [email protected]
    Dr. Norrima Binti Mokhtar
    Department of Electrical Engineering, University of Malaya, Malaysia
    [email protected]
    Dr. Mohamadariff
    Department of Electrical Engineering, University of Malaya, Malaysia
    [email protected]

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