FPGA Implementation of Reversible Adder/Subtractor

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FPGA Implementation of Reversible Adder/Subtractor

Author : Gowthami. P and R.V.S. Satyanarayana
Volume 7 No.2 July-December 2018 pp 16-20

Abstract

This work presents the new design of the reversible adder/subtractor circuit. The proposed design of reversible adder/subtractor is compared to the existing counterpart in terms of design constraints such as the total number of reversible gates, no. of constant inputs and quantum cost. The delay and power of the proposed reversible adder/subtractor circuit were calculated, compared with existing reversible and conventional adder/subtractors.

Keywords

Reversible Adder/Subtractor, Reversible gates

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References

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