Back to Journal

Home»Articles»Implementation of Digital Pulse Width Modulators Using Frequency Divider Method in FPGA

JournalCover

Asian Journal of Engineering and Applied Technology (AJEAT)

Editor Dr. Seshadri Ramkumar
Print ISSN : 2249-068X
Frequency : Quarterly

Implementation of Digital Pulse Width Modulators Using Frequency Divider Method in FPGA

Author : D. Ramesh Babu and S.Karunakaran
Volume 3 No.1 January-June 2014 pp 31-35.

Abstract

The Digital pulse width modulators are used for digital control applications. When the requirement of clock frequency exceeds the required limit the switching frequency of the power converter also increased. In this paper a new architecture for digital pulse width modulator is proposed. The proposed method is based on digital clock manager which is present in the Spartan 3 FPGA. The architecture will be implemented in FPGA Spartan 3 and the performances are verified.

Keywords

DPWM- Digital Pulse Width Modulator, FPGAField Programmable Gate Array, DCM- Digital Clock Manager, and Phase shift

Full Text:

References

The Research Publication