Asian Journal of Computer Science and Technology (AJCST)
Performance Improvement of Antilogarithmic Converter Using 28 Regions Error Correction SchemeAuthor : A. T. A. Kishore Kumar and R. Seshasayanan
Volume 8 No.3 Special Issue:June 2019 pp 25-29
Logarithmic conversion is a significant portion of numerous digital signals processing system and other applications. The anti logarithmic transformation presented in this paper is able to support the anti logarithmic conversion of data with the number of bits up to thirty-two. An efficient FPGA hardware implementation of logarithmic operations is an alternative option used in arithmetic operations. In this paper, we implemented an efficient anti logarithmic converter using FPGA. This implementation is compared with 28 regions error correction scheme. The proposed hardware architecture having less area, delay with less error cost. This design is implemented using HDL tool and synthesized using Xilinx CAD tool. The implementation has with respect to existing antilog converter.
Anti logarithmic Converter, Logarithmic Number System (LNS), Efficient FPGA, Shift-And-Add Operation
 J. N. Mitchell Jr., “Computer Multiplication and Division Using Binary Logarithms”, IRE Trans. Electronic Computers, Vol. 11, pp. 512-517, Aug. 1962.
 E. L. Hall, D.D. Lynch, and S.J. Dwyer III, “Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications”, IEEE Trans. Computers, Vol. 19, pp. 97-105, Feb. 1970.
 J. M. Muller, Elementary Functions: Algorithms and Implementation, Birkhauser, 1997.
 M. J. Schulte and E.E. Swartzlander Jr., “Hardware Designs for Exactly Rounded Elementary Functions”, IEEE Trans. Computers, Vol. 43, No. 8, pp.964-973, Aug. 1994.
 M.J. Schulte and J.E. Stine, “Symmetric Bipartite Tables for Accurate Function Approximation”, Proc. 13th Symp. Computer Arithmetic, pp. 175- 183, 1997.
 M.J. Arnold and C. Walter, Unrestricted Faithful Rounding Is Good Enough for Some LNS Applications, Proc. 15th IEEE Symp. Computer Arithmetic, pp. 237-246, June 2001.
 V. Paliouras and T. Stouraitis, “Low-Power Properties of the Logarithmic Number System”, Proc. 15th IEEE Symp. Computer Arithmetic, pp. 229-236, June 2001.
 K.H. Abed and R.E. Siferd, “CMOS VLSI Implementation of 16-Bit Logarithm and Anti-Logarithm Converters”, Proc. IEEE Midwest Symp. Circuits and Systems, pp. 776-779, Aug. 1999.
 K.H. Abed and R.E. Siferd, “CMOS VLSI Implementation of a 32-Bit Logarithmic Converter”, IEEE Trans. Computers, submitted.
 S.W. Smith, The Scientist and Engineer’s Guide to Digital Signal Processing, San Diego, Calif.: California Publishing, 1997.
 E. L. Hall, D. D. Lynch and S. J. Dwyer III. “Generation of Products and Quotients using Approximate Binary Logarithms for Digital Filtering Applications,” IEEE Transactions on Computers, Vol. C-19, No. 2, pp. 97-105, February 1970.
 K. H. Abed and R. E. Sifred, “CMOS VLSI Implementation of a Low-Power Logarithmic Converter,” IEEE Transactions on Computers, Vol. 52, No. 11, pp. 142 1-1433, November 2003.
 K. H. Abed and R. E. Sifred, “VLSI Implementation of a Low-Power Antilogarithmic Converter,” IEEE Transactions on Computers, Vol. 52, No. 9, pp. 1221-1228, September 2003.