Performance Improvement of Antilogarithmic Converter Using 28 Regions Error Correction Scheme
Author : A. T. A. Kishore Kumar and R. SeshasayananVolume 8 No.3 Special Issue:June 2019 pp 25-29
Abstract
Logarithmic conversion is a significant portion of numerous digital signals processing system and other applications. The anti logarithmic transformation presented in this paper is able to support the anti logarithmic conversion of data with the number of bits up to thirty-two. An efficient FPGA hardware implementation of logarithmic operations is an alternative option used in arithmetic operations. In this paper, we implemented an efficient anti logarithmic converter using FPGA. This implementation is compared with 28 regions error correction scheme. The proposed hardware architecture having less area, delay with less error cost. This design is implemented using HDL tool and synthesized using Xilinx CAD tool. The implementation has with respect to existing antilog converter.
Keywords
Anti logarithmic Converter, Logarithmic Number System (LNS), Efficient FPGA, Shift-And-Add Operation
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